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V827464N24S 2.5 VOLT 64M x 72 HIGH PERFORMANCE REGISTERED ECC DDR SDRAM MODULE
PRELIMINARY
CILETIV LESO M
Features
184 Pin Registered 67,108,864 x 72 bit Organization DDR SDRAM Modules Utilizes High Performance 64M x 4 DDR SDRAM in TSOPII-66 Packages Single +2.5V ( 0.2V) Power Supply Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All Inputs, Outputs are SSTL-2 Compatible 8192 Refresh Cycles every 64 ms Serial Presence Detect (SPD) DDR SDRAM Performance
Component Used
tCK tAC Clock Frequency (max.) Clock Access Time CAS Latency = 2.5
Description
The V827464N24S memory module is organized 67,108,864 x 72 bits in a 184 pin memory module. The 64M x 72 memory module uses 18 MoselVitelic 64M x 4 DDR SDRAM. The x72 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
-6
166
-7
143
-75
133
-8
125
(PC333) (PC266A) (PC266B) (PC200)
6
7
7.5
8
Module Speed
A1 B0 B1 C0 PC1600 (100MHz @ CL2) PC2100B (133MHz @ CL2.5) PC2100A (133MHz @ CL2) PC2700 (166MHz @ CL2.5)
Standard Module
Low Profile Module
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Part Number Information
V
MOSEL VITELIC MANUFACTURED
8
2
74
64
N2
4
S
X
T
(X) - XX
DDR SDRAM 2.5V WIDTH DEPTH 184 PIN Registered DIMM X4 COMPONENT REFRESH RATE 8K
SPEED A1 (100MHz@CL2) B0 (133MHz@CL2.5) B1 (133MHz@CL2) C0 (166MHz@CL2.5)
G: Gold lead Regular Profile L: Gold lead Low Profile COMPONENT PACKAGE, T = TSOP COMPONENT REV LEVEL STTL 4 BANKS
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Block Diagram
VSS RS0 DQS0
DQ0 DQ1 DQ2 DQ3 DQS CS I/O3 I/O2 D0 I/O1 I/O0 DM
DQS9 (DM0)
DQ4 DQ5 DQ6 DQ7
DQS CS I/O3 I/O2 D9 I/O1 I/O0
DM
DQS1
DQ8 DQ9 DQ10 DQ11 DQS CS I/O3 I/O2 D1 I/O1 I/O0 DM
DQS10 (DM1)
DQ12 DQ13 DQ14 DQ15
DQS CS DM I/O3 I/O2 D10 I/O1 I/O0
DQS2
DQ16 DQ17 DQ18 DQ19 DQS CS I/O3 I/O2 D2 I/O1 I/O0 DM
DQS11 (DM2)
DQ20 DQ21 DQ22 DQ23
DQS CS DM I/O3 I/O2 D11 I/O1 I/O0
DQS3
DQ24 DQ25 DQ26 DQ27 DQS CS I/O3 I/O2 D3 I/O1 I/O0 DM
DQS12 (DM3)
DQ28 DQ29 DQ30 DQ31
DQS CS DM I/O3 I/O2 D12 I/O1 I/O0
DQS4
DQ32 DQ33 DQ34 DQ35 DQS CS I/O3 I/O2 D4 I/O1 I/O0 DM
DQS13 (DM4)
DQ36 DQ37 DQ38 DQ39
DQS CS DM I/O3 I/O2 D13 I/O1 I/O0
DQS5
DQ40 DQ41 DQ42 DQ43 DQS CS I/O3 I/O2 D5 I/O1 I/O0 DM
DQS14 (DM5)
DQ44 DQ45 DQ46 DQ47
DQS CS DM I/O3 I/O2 D14 I/O1 I/O0
DQS6
DQ48 DQ49 DQ50 DQ51 DQS CS I/O3 I/O2 D6 I/O1 I/O0 DM
DQS15 (DM6)
DQ52 DQ53 DQ54 DQ55
DQS CS DM I/O3 I/O2 D15 I/O1 I/O0
SerialPD SCL WP A0 SA0 V DDSPD VD D /V DDQ A1 SA1 A2 SA2 SDA
DQS7
DQ56 DQ57 DQ58 DQ59 DQS CS I/O3 I/O2 D7 I/O1 I/O0 DM
DQS16 (DM7)
DQ60 DQ61 DQ62 DQ63
DQS CS DM I/O3 I/O2 D16 I/O1 I/O0
DQS8
CB0 CB1 CB2 CB3 DQS CS I/O3 I/O2 D8 I/O1 I/O0 DM
DQS17 (DM8)
CB4 CB5 CB6 CB7
SPD D0-D17 D0-D17
DQS CS DM I/O3 I/O2 D17 I/O1 I/O0
VREF V SS
D0-D17 D0-D17
S0 BA0-BAN A0-A13 RAS CAS CKE0 WE PCK PCK R E G I S T E R
RS0A RS0B RBA0-RBAn RA0-RA12 RRAS RCAS RCKE0A RCKE0B RWE RESET BA0-BAn:SDRAMsDQ0-D17 A0-An:SDRAMsD0-D17 RAS:SDRAMsD0-D17 CAS:SDRAMsDQ0-D17 CKE:SDRAMsD0-D8 CKE:SDRAMsD9-D17 WE:SDRAMsD0-D17
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Pin Configurations (Front Side/Back Side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 Vss A1 CB0* CB1* VDD DQS8* A0 CB2* VSS CB3* BA1 Key Key DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ BA2* DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0* CK0* VSS DM8* A10 CB6* VDDQ CB7* Key key VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Notes:
* These pins are not used in this module.
Pin
Pin Description
Power Supply DQs Power Supply Ground Reference Power Supply Power Supply for SPD E2 PROM Address Inputs E2 PROM Clock E2 PROM Data I/O VDD Identification Flag Do not Use No Connection
Pin Names
Pin
CK1, CK1, CK2, CK2 CS0 CKE0 RAS, CAS, WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7
VDD
Pin Description
Differential Clock Inputs Chip Select Input Clock Enable Input Commend Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask
VDDQ VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC
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C0 (PC2700 @ CL2.5)
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Serial Presence Detect Information
Bin Sort: A1 (PC1600 @ CL2) B0 (PC2100B @ CL2.5) B1 (PC2100A @ CL2)
Function Supported Byte #
0
Hex value A1 B0
80h
Function described
Defines # of Bytes written into serial memory at module manufacturer Total # of Bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly .........Data width of this assembly VDDQ and interface standard of this assembly DDR SDRAM cycle time at CAS Latency =2.5 DDR SDRAM Access time from clock at CL=2.5 DIMM configuration type(Non-parity, Parity, ECC) Refresh rate & type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address DDR SDRAM device attributes : Burst lengths supported DDR SDRAM device attributes : # of banks on each DDR SDRAM DDR SDRAM device attributes : CAS Latency supported DDR SDRAM device attributes : CS Latency DDR SDRAM device attributes : WE Latency DDR SDRAM module attributes
A1
B0
B1
C0
B1
C0
128bytes
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
256bytes SDRAM DDR 13 11 1 Bank 72 bits SSTL 2.5V 8ns 7.5ns 7ns 6ns 80h 80h 75h 75h
08h 07h 0Dh 0Bh 01h 48h 00h 04h 70h 75h 02h 82h 04h 04h 01h 60h 70h
0.8ns 0.75n 0.75n 0.70n Non-parity, ECC 7.8us & Self refresh x4 x4 tCCD=1CLK 2,4,8 4 banks 2,2.5 0CLK 1CLK Registered address& control inputs and On-card DLL +/-0.2V voltage tolerance 10ns 10ns 7.5ns 7.5ns
16 17 18 19 20 21
0Eh 04h 0Ch 01h 02h 26h
22 23 24 25 26 27
DDR SDRAM device attributes : General DDR SDRAM cycle time at CL =2 DDR SDRAM Access time from clock at CL =2 DDR SDRAM cycle time at CL =1.5 DDR SDRAM Access time from clock at CL =1.5 Minimum row precharge time (=tRP)
00h A0h 80h A0h 75h 00h 00h 50h 50h 50h 48h 75h 75h 75h 70h
0.8ns 0.75ns 0.75ns 0.70ns 20ns 20ns 20ns 18ns
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Serial Presence Detect Information (cont.)
Function Supported Byte #
28 29 30 31 32 33 34 35 36-40 41
Hex value A1
3Ch 50h 32h
Function described
Minimum row activate to row active delay(=tRRD ) Minimum RAS to CAS delay(=tRCD ) Minimum active to precharge time(=tRAS) Module Row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset information (may be used in future) SDRAM device minimum active to active/auto-refresh time (=tRC) SDRAM device minimum active to autorefresh to active/auto-refresh time (=tRFC ) SDRAM device maximum device cycle time (=tCK MAX) SDRAM device maximum skew between DQS and DQ signals (=tDQSQ) SDRAM device maximum read datahold skew factor (=tQHS) SPD data revision code Checksum for Bytes 0 ~ 62 Manufacturer JEDEC ID code ....... Manufacturer JEDEC ID code Manufacturing location
A1
15ns 20ns 50ns
B0
15ns 20ns 45ns
B1
15ns 20ns 45ns
C0
12ns 18ns 42ns
B0
3Ch 50h 2Dh 40h
B1
38h 48h 2Dh
C0
30h 48h 2Ah
256MB 1.1ns 1.1ns 0.6ns 0.6ns 0.9ns 0.9ns 0.5ns 0.5ns 70ns 65ns 65ns 60ns 46h 41h 0.9ns 0.9ns 0.5ns 0.5ns 0.75ns 0.75ns 0.45ns 0.45ns B0h B0h 60h 60h 90h 90h 50h 50h
90h 90h 50h 50h 00h 3Ch
75h 75h 45h 45h
3Ch
42
80ns
75ns
75ns
72ns
50h
4Bh
4Bh
48h
43 44
12ns 0.6ns
12ns 0.5ns
12ns 0.5ns
12ns 0.45ns
30h 3Ch
30h 32h
30h 32h
30h 2Dh
45 62 63 64 65 -71 72
1ns
0.75ns 0.75ns 0.60ns Initial release Mosel Vitelic
A0h
75h 00h
75h
60h
38h
73h 40h 00h
2Ah
9Ch
02=Taiwan 05=China 0A=S-CH V827464N24S 0 0 Undefined Undefined 00 00 00h 00h
73-90 91 92 93 94 95~98
Module part number (ASCII) Manufacturer revison code (For PCB) Manufacturer revison code (For component) Manufacturing date (Week) Manufacturing date (Year) Assembly serial #
99~127 Manufacturer specific data (may be used in future) 128~25 Open for customer use 5
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DC Operating Conditions
(TA = 0 to 70C, Voltage referenced to VSS = 0V)
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage I/O Termination Voltage Reference Voltage Input Leakage Current Output Leakage Current Output High Current (VOUT = 1.95V) Output Low Current (VOUT = 0.35V)
Symbol
VDD VDDQ VIH VIL VTT VREF II IOz IOH IOL
Min
2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 1.15 -2 -5 -16.8 16.8
Typ.
2.5 2.5 VREF 1.25 -
Max
2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 1.35 2 5 -
Unit
V V V V V V A A mA mA
Note
1
2
3
Notes: 1. VDDQ must not exceed the level of VDD . 2. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ.
AC Operating Conditions
(TA = 0 to 70 C, Voltage referenced to VSS = 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC) VIL(AC) VID(AC) VIX(AC)
Min
VREF + 0.31
Max
Unit
V
Note
VREF - 0.31 0.7 0.5*VDDQ-0.2 VDDQ + 0.6 0.5*VDDQ+0.2
V V V 1 2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
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(VDD = 2.5V, VDDQ = 2.5V, TA = 25C, f = 1MHz)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CS0) Input capacitance (CLK1, CLK2) Data & DQS input/output capacitance (DQ 0~DQ63) Input capacitance (DM0~DM8)
CILETIV LESO M
AC Operating Test Conditions (TA = 0 to 70C, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (R S) Output Load Capacitance for Access Time Measurement (C L)
Value
VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30
Unit
V V V V V V V V/ns Ohm Ohm pF
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Symbol
CIN1 CIN2 CIN3 CIN4 COUT CIN5
Min
60 40 40 30 10 10
Max
75 48 48 32 12 12
Unit
pF pF pF pF pF pF
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DDR SDRAM IDD SPEC TABLE
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7 A1 PC1600@CL2 1640 1860 280 640 640 280 1100 2700 2360 3260 54 33 4600 B0 PC2100B@CL2.5 1860 2180 380 640 740 380 1280 3440 3080 3440 54 33 5400 B1 PC2100A@CL2 1860 2180 380 640 740 380 1280 3440 3080 3440 54 33 5400 C0 PC2700@CL2.5 1990 2540 460 280 190 370 550 1700 1600 1800 30 33 6400
Unit
mA mA mA mA mA mA mA mA mA mA mA mA mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25' C 2. Worst Case : Vdd = 2.7V, T= 10' C 3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 4. Timing patterns - DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing *50% of data changing at every burst Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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AC Characteristics (AC operating conditions unless otherwise noted)
(PC333) Parameter
Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS CAS Latency = 2.5 CAS Latency = 2 tCH tCL tAC tDQSCK tDQSQ tQH tHP tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST
(PC266A) Min
65 75 45 20 15 1 20 15 1 35
(PC266B) Min
65 75 45 20 15 1 20 15 1 35
(PC200) Min
70 80 50 20 15 1 20 15 1 35
Symbol
tRC tRFC tRAS tRCD tRRD tCCD tRP tWR tDRL tDAL tCK
Min
60 72 42 18 12 1 18 12 1 35
Max
120K -
Max
120K -
Max
120K -
Max Unit Note
120K ns ns ns ns ns CLK ns ns CLK ns
6 7.5 0.45 0.45 -0.75 -0.75 tHPmin -0.75ns tCH/L min 0.75 0.75 0.8 0.8 0.4 0.4 0.75 0.45 0.45 1.75 0.9 0.4 0
12 12 0.55 0.55 0.75 0.75 0.45 -
7 7.5 0.45 0.45 -0.75 -0.75 tHPmin -0.75ns tCH/L min 0.9 0.9 1.0 1.0 2.2 0.4 0.4 0.75 0.5 0.5 1.75 0.9 0.4
12 12 0.55 0.55 0.75 0.75 0.5 -
7.5 10 0.45 0.45 -0.75 -0.75 tHPmin -0.75ns tCH/L min 0.9 0.9 1.0 1.0 2.2 0.4 0.4 0.75 0.5 0.5 1.75 0.9 0.4
12 12 0.55 0.55 0.75 0.75 0.5 -
8 10 0.45 0.45 -0.8 -0.8 tHPmin -0.75ns tCH/L min 1.1 1.1 1.1 1.1 0.4 0.4 0.75 0.6 0.6 2 0.9 0.4
12 12 0.55 0.55 0.8 0.8 0.6 -
ns ns CLK CLK ns ns ns ns 1
Clock Half Period
-
-
-
-
ns
1
Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width CLK to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time
0.6 0.6 1.25 1.1 0.6 -
0.6 0.6 1.25 1.1 0.6
0.6 0.6 1.25 1.1 0.6
0.6 0.6 1.25 1.1 0.6
ns ns ns ns ns CLK CLK CLK ns ns ns CLK CLK
2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6 6
7 7
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AC Characteristics (cont.)
(PC333) Parameter
Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Power Down Exit Time Exit Self Refresh to Non-Read Command Exit Self Refresh to Read Command Average Periodic Refresh Interval
(PC266A) Min
0 0.25 0.4 2 10 75 200 -
(PC266B) Min
0 0.25 0.4 2 10 75 200 -
(PC200) Min
0 0.25 0.4 2 10 80 200 -
Symbol
tWPRES tWPREH tWPST tMRD tPDEX tXSNR tXSRD tREFI
Min
0.25 0.4 2 10 75 200 200 -
Max
0.6 7.8
Max
0.6 7.8
Max
0.6 7.8
Max Unit Note
0.6 7.8 CLK CLK CLK CLK ns ns CLK us 8
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns 5. CK, CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to V SS Output Short Circuit Current Power Dissipation Soldering Temperature * Time
Symbol
TA TSTG VIN , V OUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 8 260 * 10
Unit
C C V V V mA W C * Sec
Note: Operation at above absolute maximum rating can adversely affect device reliability
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.079 (2.00) R (4X)
.098 (2.50) D (2X) .091 (2.30) TYP.
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN
CILETIV LESO M
Module Dimensions (Standard)
FRONT VIEW
5.256 (133.50) 5.244 (133.20) .125 (3.175) MAX
U10 U1 U2 U3 U4 U5 U6 U7 U8 U9
1.705 (43.31) 1.695 (43.05)
U11
U12
U13 .700 (17.78) TYP.
PIN 1
.091 (2.30) TYP. .050 (1.27) TYP. 2.55 (64.77) .040 (1.02) TYP. .250 (6.35) TYP.
.035 (0.90) R .394 (10.00) TYP. 1.95 (49.53) 4.750 (120.65)
.054 (1.37) .046 (1.17)
PIN 92
BACK VIEW
U14
U15
U16
U17
U18
U19
U20
U21
U22
PIN 184
PIN 93
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.079 (2.00) R (4X)
.098 (2.50) D (2X) .091 (2.30) TYP.
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN
CILETIV LESO M
Module Dimensions (Low Profile)
FRONT VIEW
5.256 (133.50) 5.244 (133.20)
.125 (3.175) MAX
U11 U1 U2 U3 U4 U5 U6 U7 U8 U9
1.205 (30.61) 1.195 (30.35)
U12
.700 (17.78) TYP.
PIN 1
.091 (2.30) TYP. .050 (1.27) TYP. 2.55 (64.77) .040 (1.02) TYP. .250 (6.35) TYP.
.035 (0.90) R .394 (10.00) TYP. 1.95 (49.53) 4.750 (120.65)
.054 (1.37) .046 (1.17)
PIN 92
BACK VIEW
U13 U14 U15 U16 U17 U18 U19 U20 U21 U22
U10
PIN 184
PIN 93
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Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC2100 or PC1600 (refer to MVI datasheet) DIMM manufacture date code
V827464N24SXXX-XX PC2100R-2533-XXX-X XXXX-XXXXXXX Assembly in Taiwan
512MB
PC2100 R - 2533 - XX X - X
REGISTERED DIMM CL = 2.5 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) Gerber file JEDEC SPD Revision Cycle Time
Module Density
MOSEL VITELIC
Part Number Criteria of PC2700
DIMM manufacture date code
V827464N24SXX-XX 512MB CLXX PC2700R-2533-0-XX XXXX-XXXXXXX Assembly in Taiwan
CAS Latency
PC2700 R - 2533 - 0 - X
REGISTERED DIMM CL = 2.5 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) SPD Revision
X
Revision number of the reference design used "1" : 1st Revision "2" : 2nd Revision blank : not applicable
Gerber file used for this design "A" : Reference design for raw card A is used for this assembly "B" : Reference design for raw card B is used for this assembly "C" : Reference design for raw card C is used for this assembly "Z" : None of the reference design were used for this assembly
V827464N24S Rev. 1.0 August 2002
14
V827464N24S
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
CILETIV LESO M
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
SINGAPORE
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UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516
JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
U.S. SALES OFFICES
CENTRAL / EAST
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029
(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
V827464N24S Rev. 1.0 August 2002
15

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